The present invention relates generally to the field of semiconductor devices. More particularly, the present invention relates to generation of bit line voltages in a memory device.
Cascode amplifiers are known in the art for converting current to voltage. Current to voltage conversion is particularly useful when a comparison between a first current and a second current is required. The reason is that voltage comparators, such as operational amplifiers, for example, are readily available for comparing two voltage values. Accordingly, the conventional approach in comparing two current values involves first converting the current values to voltage values, and then comparing the voltage values using an operational amplifier.
In practice, the comparison of current values is useful in a wide variety of applications. For example, often the state of a device or component is indicated by the current associated with the device or component. In the case of a memory device, for example, the state of a memory cell within the memory device is typically indicated by the current drawn by the memory cell. For example, a memory cell may be defined as a xe2x80x9cprogrammedxe2x80x9d cell if the memory cell current is below a reference current value. Conversely, a memory cell may be defined as an xe2x80x9cerasedxe2x80x9d cell if the memory cell current is above the reference current value. In this example, a comparison between the detected memory cell current and the reference current is needed to determine the state of the memory cell. As pointed out above, in practice, the memory cell current and the reference current are first converted to corresponding voltage values, and then the converted voltage values are compared using an operational amplifier.
Known cascode amplifiers suffer from several problems. First, while it is desirable to stabilize the voltage at the node connecting the cascode amplifier to the memory cell (i.e., the bit line voltage), it is often difficult to do so. The reason is that due to variations, such as variations in supply voltage, process and temperature, the threshold voltage (VT) of the transistors implemented in the cascode amplifier may have a wide varying range. Since the transistors implemented in the cascode amplifier are typically of different types (e.g., have different threshold voltage ranges), the transistors do not closely track each other with respect to these variations, thereby resulting in a bit line voltage which varies greatly and depends largely on such variations. An unstable bit line voltage may lead to an unreliable output voltage from the cascode amplifier. Accordingly, there exists a strong need in the art to overcome deficiencies of known cascode amplifier circuits, such as those described above, and to provide fast, stable and accurate bit line voltages.
The present invention addresses and resolves the need in the art for a cascode amplifier circuit which generates a fast, stable and accurate bit line voltage. According to one exemplary embodiment, a cascode amplifier circuit comprises a first transistor having a source connected to a bit line voltage and a drain connected to an output voltage. The first transistor may, for example, be an enhancement mode FET, and, by way of example, the first transistor can be connected to a supply voltage through an enable transistor and a resistor.
The exemplary embodiment also comprises a differential circuit having an inverting input connected to the bit line voltage, a non-inverting input connected to a reference voltage, and an output connected to a gate of the first transistor. The differential circuit operates as a negative feedback differential amplifier. In one embodiment, the inverting input of the differential circuit comprises a second transistor, and the non-inverting input of the differential circuit comprises a third transistor, where, by way of illustration, a gate of the second transistor is connected to the bit line voltage, a drain of the second transistor is connected to the gate of the first transistor, and a gate of the third transistor is connected to the reference voltage. In this particular embodiment, the drain of the second transistor can also be connected to a supply voltage through one resistor, and a drain of the third transistor is connected to the supply voltage through another resistor. In one embodiment, the bit line voltage is connected to a memory cell through a selection circuit, where, for example, the memory cell has a source coupled to ground. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.